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Computer Laboratory
Andrew West |
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I'm three years into my PhD research in the Computer Architecture Group at the Computer Laboratory, supervised by Dr. Simon Moore.
My current work involves developing circuit-level designs and coding techniques to reduce the cost of synchronisation
in multi-channel interconnects. In particular this research considers
multi-wavelength optical interconnects and the development of efficient
hardware implementations for this application domain.
Between July 2003 and Nov 2004, I was involved in the Scale-Comm project.
This led to the silicon implementation of the Lochside low-latency virtual-channel network-on-chip design.
Please refer to Dr. Robert Mullins' summary page for more information on this test chip.
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Publications
R. Mullins, A. West and S. Moore, The Design and Implementation of a Low-Latency On-Chip Network, in Proceedings of the 11th Asia and South Pacific Design Automation Conference, January 2006.
G.F. Roberts, R.V. Penty, I.H. White, A. West and S.W. Moore, Multi-wavelength data encoding for improved input power dynamic range in semiconductor optical amplifier switches, The 18th Annual Meeting of the IEEE Lasers and Electro-optics society (LEOS), Sydney, Australia, October 2005.
A. West, S.W. Moore, M.W. Dales and M. Glick, Multi-Wavelength Coding for Packet-Switched Optical Interconnects, London Communications Symposium, September 2005.
R. Mullins, A. West and S.W. Moore, Low-Latency Virtual-Channel Routers for On-Chip Networks, in Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), June 2004.
Contact
E-mail: Andrew.West![[]](sym.gif)
cl.cam.ac.uk
Room SE14
University of Cambridge Computer Laboratory
William Gates Building
15 JJ Thomson Avenue
Cambridge
CB3 0FD
