CV2 FOR FPGA

CV2 can be used for ASICs or FPGAs. Output from CV2 is a Verilog netlist. This can be converted to EDIF or XNF (Xilinx Net List Format) using TT CVNL. Please also see the CVNL Manual .

The source Verilog needs to follow certain rules before it can become an FPGA device. In general, we have the following basic steps:

• Partition your Verilog to include a module which is a feasible FPGA top level chip. This must include a pad for each port, or multiple pads for bus ports.
• Compile the Verilog using CV2.100 with `-flatten' to generate a flattened Verilog netlist (.vnl file).
• Generate target netlist such as XNF (Xilinx Netlist Format) from the netlist using CVNL.

Pads

The Verilog must contain a module which is the top level FPGA model, with a name such as MYCHIP. The ports of the module will become the pins of the FPGA device. All pins need pad instantiations. Note that the `-genpadring' mode of running CV2.100 may help generate a rough pad ring to start with.

Here is an example chip.

   module MYCHIP(a_p, b_p, ...

     wire a;
     input a_p;
     IBUF pada (a_p, a);

     wire b;
     output b_p;
     OBUF padb (b_p, b);
  
     // more pads go here

     MYCHIPCORE mychipcore(.a(a), .b(b), ....);

  endmodule

The port names have, by convention, been given a suffix of `_p', but this is not required. Each input or output must go through a pad.

If the pad instance name has a the form `pNNN' where `NNN' is an integer then the CVNL tool will lock down the port to a pin on the chip. For first time layouts, normal practice will be not to lock down any ports to facilitate optimal pad placement by the FPGA tools. For pin-grid array devices, the pad instance name must have the form `p_XY', where `X' and `Y' are a letter and a one or two digit number.

In the example, all of the core logic of the device has been placed in a module, although this is normal practice, it is not required and any amount of logic may be present at the top level.

Busses

When busses are to be brought in and out of a chip, they must be manually split into separate pads. For example

   module MYCHIP(a_p, ...
     wire [2:0] a;
     input [2:0] a_p;
     IBUF pada0 (a_p[0], a[0]);
     IBUF pada1 (a_p[1], a[1]);
     IBUF pada2 (a_p[2], a[2]);

Global Clock Networks

    input clock_p;
    wire clock_in, clk;

    IBUF p30 (clock_p, clock_in);
    GCLK gclk (clk, clock_in);

    always @(posedge clk) ....

On the 4000 series Xilinx, the generic buffer BUFG can be used instead of specifc buffers, such as BUFGP_TL and the router tools will use an appropriate buffer. However, for direct input, a pad is not needed and the first alternative below is used. To invert the clock, the second alternative can be used.

`ifdef clock_not_inverted
  BUFGP_BR clkbuf(clk, clk_p);  /* pin 57 on 84 pin pack */
  EXTPIN p57(clk_p);
`else
  wire clk_in, clk_inv;  // two intermediate signals
  IBUF p57(clk_p, clk_inv);
  INV(clk_in, clk_inv);
  BUFG(clk, clk_in);
`endif

Hard Macros

Many FPGAs have RAM and ROM and other structures that it is desireable to access as hard macros. Adders and multipliers are also generally available.

Such hard macros can either be instantiated directly by the user in the source Verilog, much in the way that the pads are. Alternatively, some macros are generated automatically by CV2.

Local users, please see x4rams and xcadders for 4000 series hard macros at the moment.