Technical reports
The semantics of VHDL with Val and Hol:
towards practical verification tools
John Peter Van Tassell
June 1990, 77 pages
DOI: 10.48456/tr-196
Abstract
The VHSIC Hardware Description Language (VHDL) is an emerging standard for the design of Application Specific Integrated Circuits. We examine the semantics of the language in the context of the VHDL Annotation Language (VAL) and the Higher Order Logic (HOL) system with the purpose of proposing methods by which VHDL designs may be converted into these two forms for further validation and verification. A translation program that utilizes these methods is described, and several comprehensive VHDL design examples are shown.
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@TechReport{UCAM-CL-TR-196, author = {Van Tassell, John Peter}, title = {{The semantics of VHDL with Val and Hol: towards practical verification tools}}, year = 1990, month = jun, url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-196.pdf}, institution = {University of Cambridge, Computer Laboratory}, doi = {10.48456/tr-196}, number = {UCAM-CL-TR-196} }