The following exercises are extracted in HTML from the postscript notes on this web page.
Exercise: Write down the resolution function for a 6 value logic system where the two new states are a weak logic zero and a weak logic one (This is useful for pullup or pulldown resistors used in open collector logic etc). Actually, there maybe more than one sensible resolution function.
Exercise: Consider whether the 6 value logic system can model resistors in series with nets, rather than simply resistors with one end to the power supply. Explain how such series resistors can form part of a poor-man's tri-state system.
Exercise: Consider the truth table for an XOR gate under the four value logic system when the two inputs are connected together. How does this reflect on the power of the four value logic system ?
Exercise: In certain chips, redundant circuitry is included which can be activated if their is a defect. Given that the cost of patching a broken die using an ion beam or similar to activate the redundant logic has a processing cost equal to about 100 mm2 of processed wafer, is 90 percent successful and requires 10 percent additional area in the design, for what size and type of device is it suitable ? It is necessary to make various assumptions to answer this.
Exercise: Ignoring the title, consider whether the `NAND4 Standard Cell' data sheet is intended for standard cell or gate array use ? What information about the cell is needed to prepare an audit of resources used in a design which has used this cell ? The audit refered to is typically a report generated by the CAD tools which gives summary information.
Exercise: How large a binary counter can the illustrated PAL device implement ? Check that there are sufficient product terms for the most-significant bit.
Exercise: How true is the usual model of signal delay, where the whole signal changes voltage at one time, when we use field programmable gate arrays with high track resistance ? The conductors on FPGAs consist of many sections of real metalic conductor interconnected by the user-programmed connection points. There are then considerable resistances at points along each conductor's path. How would you estimate the various delays for the staggered arrival of a signal on each part of the net ?
Exercise: Compile some simple Verilog constructs and examine the gate-level output. Try to correlate any aspect of the input specification (except bus width) with the resulting gates. Is it hard to predict how many gates you are going to generate ?
Exercise: Write a 100 percent coverage test program for a 7400 quad NAND gate.
Exercise: Consider the testability of devices with built in redundancy.
Exercise: Design a fault simulation algorithm whose expected running time is order nv where there are n nets and v vectors. Design a better algorithm.