library verilog;
use verilog.vl_types.all;
entity pc is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        new_pc          : in     vl_logic_vector(15 downto 0);
        br_unit_en      : in     vl_logic;
        pc              : out    vl_logic_vector(15 downto 0);
        increment_pc    : in     vl_logic
    );
end pc;
