library verilog;
use verilog.vl_types.all;
entity onchip_memory_1_s1_arbitrator is
    port(
        clk             : in     vl_logic;
        cpu0_instruction_master_address_to_slave: in     vl_logic_vector(15 downto 0);
        cpu0_instruction_master_read: in     vl_logic;
        d2_reset_n      : in     vl_logic;
        onchip_memory_1_s1_readdata: in     vl_logic_vector(15 downto 0);
        cpu0_instruction_master_granted_onchip_memory_1_s1: out    vl_logic;
        cpu0_instruction_master_qualified_request_onchip_memory_1_s1: out    vl_logic;
        cpu0_instruction_master_read_data_valid_onchip_memory_1_s1: out    vl_logic;
        cpu0_instruction_master_requests_onchip_memory_1_s1: out    vl_logic;
        d1_onchip_memory_1_s1_end_xfer: out    vl_logic;
        onchip_memory_1_s1_address: out    vl_logic_vector(8 downto 0);
        onchip_memory_1_s1_readdata_from_sa: out    vl_logic_vector(15 downto 0);
        onchip_memory_1_s1_reset_n: out    vl_logic
    );
end onchip_memory_1_s1_arbitrator;
