library verilog;
use verilog.vl_types.all;
entity n_105 is
    port(
        clk             : in     vl_logic;
        readdata_instr_fetch: in     vl_logic_vector(15 downto 0);
        readdata_mem_access: in     vl_logic_vector(15 downto 0);
        reset           : in     vl_logic;
        waitrequest_instr_fetch: in     vl_logic;
        waitrequest_mem_access: in     vl_logic;
        address_instr_fetch: out    vl_logic_vector(15 downto 0);
        address_mem_access: out    vl_logic_vector(15 downto 0);
        byteenable_instr_fetch: out    vl_logic_vector(3 downto 0);
        byteenable_mem_access: out    vl_logic_vector(3 downto 0);
        read_instr_fetch: out    vl_logic;
        read_mem_access : out    vl_logic;
        write_mem_access: out    vl_logic;
        writedata_mem_access: out    vl_logic_vector(15 downto 0)
    );
end n_105;
