library verilog;
use verilog.vl_types.all;
entity n_105_rom_interface is
    port(
        bus_clk2        : in     vl_logic;
        readdata2       : in     vl_logic_vector(15 downto 0);
        waitrequest2    : in     vl_logic;
        address2        : out    vl_logic_vector(9 downto 0);
        byteenable2     : out    vl_logic_vector(3 downto 0);
        read2           : out    vl_logic;
        write2          : out    vl_logic;
        writedata2      : out    vl_logic_vector(15 downto 0)
    );
end n_105_rom_interface;
