library verilog;
use verilog.vl_types.all;
entity onchip_memory_2_lane0_module is
    port(
        address         : in     vl_logic_vector(8 downto 0);
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        q               : out    vl_logic_vector(15 downto 0)
    );
end onchip_memory_2_lane0_module;
