//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera.  Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner.  Title to
//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
//their respective licensors.  No other licenses, including any licenses
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//Copying or modifying any file, or portion thereof, to which this notice
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// exemplar translate_off
`timescale 1ns / 100ps
// exemplar translate_on
module N_105_ram_interface (
                             // inputs:
                              bus_clk1,
                              clk,
                              readdata1,
                              reset,
                              waitrequest1,

                             // outputs:
                              address1,
                              byteenable1,
                              read1,
                              write1
                           );

  output  [  9: 0] address1;
  output  [  3: 0] byteenable1;
  output           read1;
  output           write1;
  input            bus_clk1;
  input            clk;
  input   [ 15: 0] readdata1;
  input            reset;
  input            waitrequest1;

  wire    [  9: 0] address1;
  wire    [  3: 0] byteenable1;
  wire             read1;
  wire             write1;
  cpu wrapper
    (
      .address1     (address1),
      .bus_clk1     (bus_clk1),
      .byteenable1  (byteenable1),
      .clk          (clk),
      .read1        (read1),
      .readdata1    (readdata1),
      .reset        (reset),
      .waitrequest1 (waitrequest1),
      .write1       (write1)
    );



endmodule

