library verilog;
use verilog.vl_types.all;
entity condition_unit is
    port(
        clk             : in     vl_logic;
        flags_in        : in     vl_logic_vector(3 downto 0);
        set_cond_en     : in     vl_logic;
        flags           : out    vl_logic_vector(3 downto 0)
    );
end condition_unit;
