library verilog;
use verilog.vl_types.all;
entity mem_access_unit is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        load_n_store    : in     vl_logic;
        contents_a      : in     vl_logic_vector(15 downto 0);
        contents_b      : in     vl_logic_vector(15 downto 0);
        ld_st_coming    : in     vl_logic;
        advance_pipeline: in     vl_logic;
        load_result     : out    vl_logic_vector(15 downto 0);
        mem_is_busy     : out    vl_logic;
        waitrequest     : in     vl_logic;
        readdata        : in     vl_logic_vector(15 downto 0);
        address         : out    vl_logic_vector(15 downto 0);
        byteenable      : out    vl_logic_vector(3 downto 0);
        read            : out    vl_logic;
        write           : out    vl_logic;
        writedata       : out    vl_logic_vector(15 downto 0)
    );
end mem_access_unit;
