library verilog;
use verilog.vl_types.all;
entity onchip_ram_lane0_module is
    port(
        clk             : in     vl_logic;
        data            : in     vl_logic_vector(7 downto 0);
        rdaddress       : in     vl_logic_vector(9 downto 0);
        rdclken         : in     vl_logic;
        reset_n         : in     vl_logic;
        wraddress       : in     vl_logic_vector(9 downto 0);
        wrclock         : in     vl_logic;
        wren            : in     vl_logic;
        q               : out    vl_logic_vector(7 downto 0)
    );
end onchip_ram_lane0_module;
