library verilog;
use verilog.vl_types.all;
entity lcd_16207_0 is
    port(
        address         : in     vl_logic_vector(1 downto 0);
        begintransfer   : in     vl_logic;
        read            : in     vl_logic;
        write           : in     vl_logic;
        writedata       : in     vl_logic_vector(7 downto 0);
        lcd_e           : out    vl_logic;
        lcd_rs          : out    vl_logic;
        lcd_rw          : out    vl_logic;
        lcd_data        : inout  vl_logic_vector(7 downto 0);
        irq             : out    vl_logic;
        readdata        : out    vl_logic_vector(7 downto 0)
    );
end lcd_16207_0;
