library verilog;
use verilog.vl_types.all;
entity onchip_memory_0 is
    port(
        address         : in     vl_logic_vector(9 downto 0);
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        writebyteenable : in     vl_logic_vector(1 downto 0);
        writedata       : in     vl_logic_vector(15 downto 0);
        readdata        : out    vl_logic_vector(15 downto 0)
    );
end onchip_memory_0;
