library verilog;
use verilog.vl_types.all;
entity alu is
    port(
        contents_a      : in     vl_logic_vector(15 downto 0);
        contents_b      : in     vl_logic_vector(15 downto 0);
        imm7            : in     vl_logic_vector(6 downto 0);
        opcode          : in     vl_logic_vector(3 downto 0);
        result          : out    vl_logic_vector(15 downto 0);
        flags           : out    vl_logic_vector(3 downto 0)
    );
end alu;
