library verilog;
use verilog.vl_types.all;
entity onchip_ram_s1_arbitrator is
    port(
        clk             : in     vl_logic;
        d2_reset_n      : in     vl_logic;
        onchip_ram_s1_readdata: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_address_to_slave: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_byteenable: in     vl_logic_vector(3 downto 0);
        uoccl_n105_0_data_master_read: in     vl_logic;
        uoccl_n105_0_data_master_write: in     vl_logic;
        uoccl_n105_0_data_master_writedata: in     vl_logic_vector(15 downto 0);
        d1_onchip_ram_s1_end_xfer: out    vl_logic;
        onchip_ram_s1_address: out    vl_logic_vector(9 downto 0);
        onchip_ram_s1_readdata_from_sa: out    vl_logic_vector(15 downto 0);
        onchip_ram_s1_reset_n: out    vl_logic;
        onchip_ram_s1_writebyteenable: out    vl_logic_vector(1 downto 0);
        onchip_ram_s1_writedata: out    vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_granted_onchip_ram_s1: out    vl_logic;
        uoccl_n105_0_data_master_qualified_request_onchip_ram_s1: out    vl_logic;
        uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1: out    vl_logic;
        uoccl_n105_0_data_master_requests_onchip_ram_s1: out    vl_logic
    );
end onchip_ram_s1_arbitrator;
