library verilog;
use verilog.vl_types.all;
entity instruction_fetch is
    port(
        pc              : in     vl_logic_vector(15 downto 0);
        next_instruction: out    vl_logic_vector(15 downto 0);
        instruction_ready: out    vl_logic;
        waitrequest     : in     vl_logic;
        readdata        : in     vl_logic_vector(15 downto 0);
        address         : out    vl_logic_vector(15 downto 0);
        byteenable      : out    vl_logic_vector(3 downto 0);
        read            : out    vl_logic
    );
end instruction_fetch;
