library verilog;
use verilog.vl_types.all;
entity write_back is
    port(
        alu_result      : in     vl_logic_vector(15 downto 0);
        alu_en          : in     vl_logic;
        load_result     : in     vl_logic_vector(15 downto 0);
        load_en         : in     vl_logic;
        bsr_en          : in     vl_logic;
        ret_addr        : in     vl_logic_vector(15 downto 0);
        dest_contents   : out    vl_logic_vector(15 downto 0);
        write_en        : out    vl_logic
    );
end write_back;
