library verilog;
use verilog.vl_types.all;
entity lcd_16207_0_control_slave_arbitrator is
    port(
        clk             : in     vl_logic;
        d2_reset_n      : in     vl_logic;
        lcd_16207_0_control_slave_readdata: in     vl_logic_vector(7 downto 0);
        uoccl_n105_0_data_master_address_to_slave: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_byteenable: in     vl_logic_vector(3 downto 0);
        uoccl_n105_0_data_master_read: in     vl_logic;
        uoccl_n105_0_data_master_write: in     vl_logic;
        uoccl_n105_0_data_master_writedata: in     vl_logic_vector(15 downto 0);
        d1_lcd_16207_0_control_slave_end_xfer: out    vl_logic;
        lcd_16207_0_control_slave_address: out    vl_logic_vector(1 downto 0);
        lcd_16207_0_control_slave_begintransfer: out    vl_logic;
        lcd_16207_0_control_slave_read: out    vl_logic;
        lcd_16207_0_control_slave_readdata_from_sa: out    vl_logic_vector(7 downto 0);
        lcd_16207_0_control_slave_wait_counter_eq_0: out    vl_logic;
        lcd_16207_0_control_slave_write: out    vl_logic;
        lcd_16207_0_control_slave_writedata: out    vl_logic_vector(7 downto 0);
        uoccl_n105_0_data_master_granted_lcd_16207_0_control_slave: out    vl_logic;
        uoccl_n105_0_data_master_qualified_request_lcd_16207_0_control_slave: out    vl_logic;
        uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave: out    vl_logic
    );
end lcd_16207_0_control_slave_arbitrator;
