library verilog;
use verilog.vl_types.all;
entity uoccl_n105_0_instruction_master_arbitrator is
    port(
        d1_onchip_memory_1_s1_end_xfer: in     vl_logic;
        d1_uoccl_n105_0_instruction_master_granted_onchip_memory_1_s1: in     vl_logic;
        d2_reset_n      : in     vl_logic;
        onchip_memory_1_s1_readdata_from_sa: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_instruction_master_address: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_instruction_master_granted_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_0_instruction_master_qualified_request_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_0_instruction_master_read: in     vl_logic;
        uoccl_n105_0_instruction_master_read_data_valid_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_0_instruction_master_requests_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_1_instruction_master_qualified_request_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_1_instruction_master_s_turn_at_onchip_memory_1_s1: in     vl_logic;
        uoccl_n105_0_instruction_master_address_to_slave: out    vl_logic_vector(15 downto 0);
        uoccl_n105_0_instruction_master_readdata: out    vl_logic_vector(15 downto 0);
        uoccl_n105_0_instruction_master_reset: out    vl_logic;
        uoccl_n105_0_instruction_master_waitrequest: out    vl_logic
    );
end uoccl_n105_0_instruction_master_arbitrator;
