//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera.  Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner.  Title to
//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
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// exemplar translate_off
`timescale 1ns / 100ps
// exemplar translate_on
module N_105_rom_interface (
                             // inputs:
                              bus_clk2,
                              readdata2,
                              waitrequest2,

                             // outputs:
                              address2,
                              byteenable2,
                              read2,
                              write2,
                              writedata2
                           );

  output  [  9: 0] address2;
  output  [  3: 0] byteenable2;
  output           read2;
  output           write2;
  output  [ 15: 0] writedata2;
  input            bus_clk2;
  input   [ 15: 0] readdata2;
  input            waitrequest2;

  wire    [  9: 0] address2;
  wire    [  3: 0] byteenable2;
  wire             read2;
  wire             write2;
  wire    [ 15: 0] writedata2;
//synthesis read_comments_as_HDL on
//  cpu wrapper
//    (
//      .address2     (address2),
//      .bus_clk2     (bus_clk2),
//      .byteenable2  (byteenable2),
//      .read2        (read2),
//      .readdata2    (readdata2),
//      .waitrequest2 (waitrequest2),
//      .write2       (write2),
//      .writedata2   (writedata2)
//    );
//
//synthesis read_comments_as_HDL off


endmodule

