library verilog;
use verilog.vl_types.all;
entity n_105_avaloninstrm_arbitrator is
    port(
        n_105_avaloninstrm_address: in     vl_logic_vector(15 downto 0);
        n_105_avaloninstrm_granted_onchip_rom_s1: in     vl_logic;
        n_105_avaloninstrm_qualified_request_onchip_rom_s1: in     vl_logic;
        n_105_avaloninstrm_read: in     vl_logic;
        n_105_avaloninstrm_read_data_valid_onchip_rom_s1: in     vl_logic;
        n_105_avaloninstrm_requests_onchip_rom_s1: in     vl_logic;
        d1_onchip_rom_s1_end_xfer: in     vl_logic;
        onchip_rom_s1_readdata_from_sa: in     vl_logic_vector(15 downto 0);
        n_105_avaloninstrm_address_to_slave: out    vl_logic_vector(15 downto 0);
        n_105_avaloninstrm_readdata: out    vl_logic_vector(15 downto 0);
        n_105_avaloninstrm_waitrequest: out    vl_logic
    );
end n_105_avaloninstrm_arbitrator;
