library verilog;
use verilog.vl_types.all;
entity uoccl_n105_0_data_master_arbitrator is
    port(
        d1_lcd_16207_0_control_slave_end_xfer: in     vl_logic;
        d1_onchip_ram_s1_end_xfer: in     vl_logic;
        lcd_16207_0_control_slave_readdata_from_sa: in     vl_logic_vector(7 downto 0);
        lcd_16207_0_control_slave_wait_counter_eq_0: in     vl_logic;
        onchip_ram_s1_readdata_from_sa: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_address: in     vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_granted_lcd_16207_0_control_slave: in     vl_logic;
        uoccl_n105_0_data_master_granted_onchip_ram_s1: in     vl_logic;
        uoccl_n105_0_data_master_qualified_request_lcd_16207_0_control_slave: in     vl_logic;
        uoccl_n105_0_data_master_qualified_request_onchip_ram_s1: in     vl_logic;
        uoccl_n105_0_data_master_read: in     vl_logic;
        uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1: in     vl_logic;
        uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave: in     vl_logic;
        uoccl_n105_0_data_master_requests_onchip_ram_s1: in     vl_logic;
        uoccl_n105_0_data_master_write: in     vl_logic;
        uoccl_n105_0_data_master_address_to_slave: out    vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_readdata: out    vl_logic_vector(15 downto 0);
        uoccl_n105_0_data_master_waitrequest: out    vl_logic
    );
end uoccl_n105_0_data_master_arbitrator;
