library verilog;
use verilog.vl_types.all;
entity cpu1_data_master_arbitrator is
    port(
        cpu0_data_master_qualified_request_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_address: in     vl_logic_vector(15 downto 0);
        cpu1_data_master_granted_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_qualified_request_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_read: in     vl_logic;
        cpu1_data_master_read_data_valid_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_requests_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_s_turn_at_onchip_memory_0_s1: in     vl_logic;
        cpu1_data_master_write: in     vl_logic;
        d1_cpu1_data_master_granted_onchip_memory_0_s1: in     vl_logic;
        d1_onchip_memory_0_s1_end_xfer: in     vl_logic;
        onchip_memory_0_s1_readdata_from_sa: in     vl_logic_vector(15 downto 0);
        cpu1_data_master_address_to_slave: out    vl_logic_vector(15 downto 0);
        cpu1_data_master_readdata: out    vl_logic_vector(15 downto 0);
        cpu1_data_master_waitrequest: out    vl_logic
    );
end cpu1_data_master_arbitrator;
