library verilog;
use verilog.vl_types.all;
entity n_105_system is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        lcd_e_from_the_lcd_16207_0: out    vl_logic;
        lcd_rs_from_the_lcd_16207_0: out    vl_logic;
        lcd_rw_from_the_lcd_16207_0: out    vl_logic;
        lcd_data_to_and_from_the_lcd_16207_0: inout  vl_logic_vector(7 downto 0)
    );
end n_105_system;
