library verilog;
use verilog.vl_types.all;
entity branch_unit is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        return_en       : in     vl_logic;
        return_addr     : in     vl_logic_vector(15 downto 0);
        imm11           : in     vl_logic_vector(10 downto 0);
        advance_pipeline: in     vl_logic;
        br_unit_en      : in     vl_logic;
        new_return_addr : out    vl_logic_vector(15 downto 0);
        pc              : out    vl_logic_vector(15 downto 0)
    );
end branch_unit;
