library verilog;
use verilog.vl_types.all;
entity shifter is
    port(
        contents_a      : in     vl_logic_vector(15 downto 0);
        imm4            : in     vl_logic_vector(3 downto 0);
        opcode          : in     vl_logic_vector(1 downto 0);
        shift_result    : out    vl_logic_vector(15 downto 0)
    );
end shifter;
