library verilog;
use verilog.vl_types.all;
entity reg_fetch is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        br_unit_en      : in     vl_logic;
        index_a         : in     vl_logic_vector(3 downto 0);
        index_b         : in     vl_logic_vector(3 downto 0);
        dest_contents   : in     vl_logic_vector(15 downto 0);
        write_en        : in     vl_logic;
        read_n_write    : in     vl_logic;
        contents_a      : out    vl_logic_vector(15 downto 0);
        contents_b      : out    vl_logic_vector(15 downto 0)
    );
end reg_fetch;
