Rosemary Francis
2004

This project has only been tested in model sim and probably wont work on the board as it probably wont fit! Try it though it might be fun to see if it works.

This Project system has two N-105s with separate instruction memory and shared data memory. It is set up to run two programs called cluster1 and cluster2. They just read and write to and from memory. It entertained me to get them to both try and write different values then imediatly read from the same location so the one that wrote first then sees the wrong value. (I think I have been working on this too long!)

Basically it tests what happens when the CPU has to wait on an "OK" (waitrequest going low) from the bus. I did also test it with shared instruction memory and interestingly, as it takes two clock cyles to read from the ROM normally and both CPUs are reading from the same address, it doesn't slow down. It just has the the read happening a clock cycle later for one of the CPUs.

With three processors sharing the same memory, performance is affected of course with the rom reading sometimes every clock cycle and sometimes every two. I ran cluster1 on it and saw the three cpus get nicely out of sync! :)

NB you can set arbitration priorities on the avalon bus so you can set which one will "win".
