opcode | assembly format | flags | meaning
-------+-----------------+-------+------------
000 00	OR 	%RA, %RB   n.z.	  ra <- ra | rb
000 01	AND 	%RA, %RB   n.z.	  ra <- ra & rb
000 10	XOR 	%RA, %RB   n.z.	  ra <- ra ^ rb
000 11	NOT 	%RA	   ....	  not ra

001 00	MOV 	%RA, %RB   ....	  ra <- rb
001 01	ADD 	%RA, %RB   nvzc	  ra <- ra + rb
001 10	SUB 	%RA, %RB   nvzc	  ra <- ra - rb
001 11	CMP 	%RA, %RB   nvzc	  ra - rb, just set flags

010 00	LSLI 	%RA, IMM4  ....	  ra <- ra << 16-IMM4
010 01	LSRI 	%RA, IMM4  ....	  ra <- ra >>> IMM4
010 10	ASRI 	%RA, IMM4  ....	  ra <- ra >> IMM4
010 11	ROTI	%RA, IMM4  ....	  ra <- ra rotated right IMM4 places

011 00	MOVI 	%RA, IMM7s ....	  ra <- #im signed
011 01	ADDI 	%RA, IMM7  nvzc	  ra <- ra + #im unsigned
011 10	SUBI 	%RA, IMM7  nvzc	  ra <- ra - #im unsigned
011 11  CMPI	%RA, IMM7s nvzc	  ra-im Flags:nvzc signed

100 00	LD 	%RA, [%RB]	  load ra <- the address held in rb
101 00	ST 	%RA, [%RB]	  store ra -> the address held in rb

110 00	BR 	IMM11		  branch to relative address
110 01	BSR 	IMM11		  as above, and R15 <- PC
110 10	RET 			  PC <- R15

111 11	IFS 	cc_IMM4		  execute next instruction iff condition is true

The condition codes for IFS are identical to the Nios processor and can be found at the end of the Nios quick reference page in the nios_documentation directory.

For LSLI and ROTI the shift is by the bottom four bits of 16-IMM4 (= -imm4)

IMM4 is an unsigned 4-bit immediate
IMM7 is an unsigned 7-bit immediate
IMM7s is a signed 7-bit immediate
IMM11 is a signed 11-bit immediate relative address, used for branching

opcode 	: instruction[4:0]
ra 	: instruction[15:12]
rb/imm4	: instruction[11:8]
imm7	: instruction[11:5]
imm11	: instruction[15:5]

Flags
n - negative
v - arithmetic overflow
z - zero
c - carry/borrow
. - undefined
