library verilog;
use verilog.vl_types.all;
entity n_105_ram_interface is
    port(
        bus_clk1        : in     vl_logic;
        clk             : in     vl_logic;
        readdata1       : in     vl_logic_vector(15 downto 0);
        reset           : in     vl_logic;
        waitrequest1    : in     vl_logic;
        address1        : out    vl_logic_vector(9 downto 0);
        byteenable1     : out    vl_logic_vector(3 downto 0);
        read1           : out    vl_logic;
        write1          : out    vl_logic
    );
end n_105_ram_interface;
