library verilog;
use verilog.vl_types.all;
entity n_105_avalonm_arbitrator is
    port(
        n_105_avalonm_address: in     vl_logic_vector(15 downto 0);
        n_105_avalonm_granted_onchip_ram_s1: in     vl_logic;
        n_105_avalonm_qualified_request_onchip_ram_s1: in     vl_logic;
        n_105_avalonm_read: in     vl_logic;
        n_105_avalonm_read_data_valid_onchip_ram_s1: in     vl_logic;
        n_105_avalonm_requests_onchip_ram_s1: in     vl_logic;
        n_105_avalonm_write: in     vl_logic;
        d1_onchip_ram_s1_end_xfer: in     vl_logic;
        d2_reset_n      : in     vl_logic;
        onchip_ram_s1_readdata_from_sa: in     vl_logic_vector(15 downto 0);
        n_105_avalonm_address_to_slave: out    vl_logic_vector(15 downto 0);
        n_105_avalonm_readdata: out    vl_logic_vector(15 downto 0);
        n_105_avalonm_reset: out    vl_logic;
        n_105_avalonm_waitrequest: out    vl_logic
    );
end n_105_avalonm_arbitrator;
