module reset_gen(clk, reset_n);

input clk;
output reset_n;

reg reset_n;
re

always@(posedge clk)
begin

	if (counter > 0 & reset_n)
		counter <= counter + 1;
	
	if (counter == 100'd0)
		reset_n <= 0;
	else
		reset_n <= 1;
		
end

endmodule