VLSI Design Errata

The following corrections should be applied to the published notes:
Page 4, last paragraph
"thick layer" rather than "think layer"
Page 9, first paragraph
"use of the word" rather than "use of the work"
Page 10, logic table for simple multiplexor
The outputs are A0..A3 rather than I0..I3
Page 16, formula for exclusive NOR
Q = ~(~A + ~B) + ~(A + B)
Page 20, first paragraph on pre-charging
"correct ratio" rather than "correct ration".
Page 28, second bullet point
"Manchester" rather than "Manchecster"
Page 36, second paragraph on driving capacitive loads
"the third a 4:f2 pull-up" rather than "the third a 4:f pull-up"
Page 51, STG for event FIFO
Replacement diagram corrects some labels and the initial positions of the tokens
Please let me know of any others! Thanks, PR.