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Part II CST SoC D/M Pack KG5 - High-Level Synthesis

  • High-level Design Capture and Synthesis
  • Start Here
  • Higher-level: Generative, Behavioural or Declarative?
  • Parellelism: The key to high performance.
  • Instruction-Level Parallelism
  • Beyond Pure RTL: Behavioural descriptions of hardware.
  • More-advanced behavioural specification:
  • A Simple Worked Example: Classical HLS of Multiply
  • Classical HLS Compiler: Operational Phases
  • Adopting a Suitable Coding Style for HLS
  • HLS Synthesisable Subset.
  • Unrolling: Trading time for space.
  • Pipelined Schedulling - One Basic Block
  • Pipelined Schedulling - Between Basic Blocks
  • HLS Functional Units (FUs)
  • Functional Unit (FU) Block Properties
  • Functional Unit (FU) Chaining
  • Discovering Parallelism: Classical HLS Paradigms
  • Memory Banking and Widening
  • Data Layout for Burrows-Wheeler Transform
  • Smith-Waterman D/P Data Dependencies
  • Polyhedral Address Mapping
  • The Perfect Shuffle Network - FFT Example
  • Kiwi: Compiling Concurrent Programs to Hardware
  • Parallel-For and Parallel-ForEach Loops
  • Classical High-Level Synthesis Example: Kiwi compilation of Sieve of Eratosthenes.
  • Profile-Directed Guidance
  • Locally-Static, Globally-Dynamic Schedulling
  • Motivation To Adopt HLS
  • Other Models of Computation: Channel Communication
  • Other Expression forms: Hardware Construction Languages
  • Other Expression forms: Logic Synthesis from Guarded Atomic Actions (Bluespec)
  • Classical Imperative/Behavioural H/L Synthesis Summary
  • Accellera IP-XACT
  • IP-XACT Tool Flow