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Part II CST SoC D/M Pack KG4 - RTL

  • RTL, Interfaces, Pipelining and Hazards
  • Protocol and Interface
  • Transactional Handshaking
  • Transactional Handshaking in RTL (Synchronous Example)
  • Architecture: Bus and Device Structure
  • A canonical D8/A16 Micro-Computer from 1980's
  • Basic Bus: One initiator (II).
  • Basic bus: Multiple Initiators (II).
  • Bridged Bus Structures.
  • Classes of On-Chip Protocol
  • Practical Bus Protocols on IP Blocks
  • BVCI Net-Level Protocol.
  • ARM AXI Bus: The Current Favourite
  • Supporting out-of-order operation using tags.
  • RTL: Register Transfer Language
  • RTL Summary View of Variant Forms.
  • Structural Verilog
  • Generative Forms
  • Structure Flattening
  • 2a/3: Continuous Assignment.
  • 2b/3: Pure RTL : unordered synchronous register transfers.
  • 3/3: Behavioural RTL
  • Comprehensive Illustrative Examples
  • Simulation And Synthesis.
  • Synthesisable RTL
  • Synthesis Example
  • Verilog RTL Synthesis Algorithm: 3-Step Recipe
  • Arrays and RAM Inference in RTL
  • Behavioural - `Non-Synthesisable' RTL
  • Further Logic Synthesis Issues
  • Simulation
  • Digital Logic Modelling
  • Event Driven Simulation
  • Compute/Commit Cycle With Delta Cycles
  • Mixed Analog/Digital Simulation (Verilog-AMS)
  • Mixed Analog/Digital Simulation: An interesting problem attributable to Zeno?
  • Higher-level Simulation
  • Hazards
  • Example: Sequential Long Multiplication
  • Hazards From Array Memories
  • Overcoming Structural Hazards using Holding Registers
  • Folding, Retiming & Recoding
  • Critical Path Timing Delay
  • Static Timing Analyser Tool
  • Back Annotation and Timing Closure
  • FIFOs
  • End of Pack
  • Conventional RTL Compared with Software
  • Conventional RTL Conclusion