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Part II CST SoC D/M Slide Pack 8 (High-Level Synthesis)

  • High-level Design Capture and Synthesis
  • Accellera IP-XACT
  • IP XACT Tool Flow
  • Higher-level: Behavioural or Declarative ?
  • Beyond Pure RTL: Behavioural descriptions of hardware.
  • More-advanced behavioural specification:
  • A Simple Worked Example: Classical HLS of Multiply
  • HLS Compiler Operational Phases
  • Adopting a Suitable Coding Style for HLS
  • HLS Synthesisable Subset.
  • Functional Block Properties
  • Discovering Parallelism: Classical HLS Paradigms
  • Polyhedral Address Mapping
  • Kiwi : Compiling Concurrent Programs to Hardware
  • Classical High-Level Synthesis Example: Kiwi compilation of Sieve of Eratosthenes.
  • Static versus Dynamic Scheduling
  • Locally-Static, Globally-Dynamic Schedulling
  • Shortcomings of Verilog and VHDL as Algorithmic Expression Languages
  • Motivation To Adopt HLS
  • Other Expression forms: Channel Communication
  • Other Expression forms: Hardware Construction Languages
  • Other Expression forms: Logic Synthesis from Guarded Atomic Actions (Bluespec)
  • Classical Imperative/Behavioural H/L Synthesis Summary