Further Synthesis Issues

There are many combinational circuits that have the same functionality.

Synthesis tools can accept additional guiding metrics from the user, that affect

• Power consumption,
• Area use,
• Performance,
• Testability.

Gate libraries have high and low drive stength forms of most gates (see later). The synthesis tool will chose the appropriate gate depending on the fanout and (estimated) net length during routing.

Some leaf cells are broadside and do not require bit-blasting.

The tool will use Quine/McCluskey, Espresso or similar for logic minimisation. Liberal use of the `x' don't care designation in the source RTL allows the synthesis tool freedom to perform this logic minimisation.

   reg[31:0] y;
   ...
   if (e1) y <= e2; 
   else if (e3) y <= e4; 
   else y <= 32'bx;              // Note, assignment of 'x' permits automated logic minimisation.

Can share sub-expressions or re-compute expressions locally. Reuse of sub-expressions is important for locally-derived results, but with today's VLSI, sending a 32 bit addition result more than one millimeter on the chip may use more power then recomputing it locally!

Can re-encode state (see later).

25: (C) 2008-16, DJ Greaves, University of Cambridge, Computer Laboratory.

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