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Digital Logic Modelling

In the four value logic system each net (wire or signal), at a particular time, has one of the following logic values:

0 logic zero
1 logic one
Z high impedance --- not driven at the moment
X uncertain --- the simulator does not know

In design specification, the letter `x' is also used to denote `dont-care', which allows efficient logic minimisation. In Verilog, the letter `x' means uncertain during simulation and `dont-care' during logic synthesis.

In this model, nets jump from one value to another in an instant. Real nets have a transit time.