The generate statements in Verilog and VHDL are clunky imperative affairs.
How much nicer it is to print out your circuit using higher-order functional programs! That's the approach of Chisel, a DSL embedded in Scala.
Lava was the first HCL of this nature: 'Lava: Hardware Design in Haskell (1998)' by Per Bjesse, Koen Claessen, Mary Sheeran.
| 29: (C) 2008-16, DJ Greaves, University of Cambridge, Computer Laboratory. | 
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