Progpagation Down a Conductor

On a chip, the speed of light can be neglected because chips are physically small, but the resistance of the aluminium conductors is sufficiently large to have an effect for critical applications, such as master clock signals.

Older technologies used polysilicon interconnections which had significant resistance and so the different gates connected to a polysilicon net would experience different arrival times of a signal at their inputs.

A conductor made of aluminium on a chip is small enough for the speed of light delay to be ignored. Its resistance is generally small enough for it to be considered at the same voltage at all points. (critical clock nets are sometimes studied in more detail).

On a circuit board, a copper conductor is often too long for the speed of propagation of signals to be neglected, but its resistance is always so low that the influence of resistance may be neglected (except for power supply traces --- but we are not interested in the speed of signals on power conductors).

In both cases, it is generally sufficient to model the propagation delay of the net as an increase in the output delay of its driver(s) using the formula below. In addition, output drivers slow down in themselves as the output net length and and fanout is increased owing to capacitance and this effect normally dominates net propagation delay. Hence the standard model above.

The upshot of this is that on a chip, we can mostly neglect the propagation aspects of delay, whereas on a circuit board, we need to model certain critical conductors as components in themselves. These have a simple delay model, whose value can be set by post routing back annotation.