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ARM AXI Bus: The Current Favourite

One AXI port if formed of five separate interfaces: two for read, three for write.

Often the address and data for write will run in lockstep, making a more natural total of four logical interfaces.

Sequential consistency: RaW and WaR hazards are immediately manifest!

AXI can be used with and without (AXI-lite) ordering tokens/tags.

AXI is widely used even for non-ARM products »ARM AXI


79: (C) 2008-16, DJ Greaves, University of Cambridge, Computer Laboratory.