A SoC consists of interconnected IP Blocks

We tour a number of IP (intellectual property) blocks. All will be targets, most will also generate interrupts and some will also be initiators.

Interupts will be conveyed by custom point-to-point nets. Data will use a 'bus'.

A bus conveyes a transaction from an initiating IP block on a target block and a response back again.

A transaction contains a command that typically selects one of the these forms:

• Single Word Write: as generated by a CPU store instruction,
• Single Word Read: ditto for CPU load,
• Burst Reads or Writes: as cache lines are loaded or evicted or from block moves (e.g. Ethernet packed DMA),
• Laned Writes: byte stores mean that only certain parts of a word are dirty,
• Load-locked: (aka load-linked) takes a lock on a memory location,
• Store-conditional: (aka store-exclusive) performs a write if lock not lost in the meantime,
• (Misc Others: Presence probe, debug access, read-ahead warm up ...)