Typical IP Blocks

We tour a number of IP (intellectual property) blocks. All will be targets, most will also generate interrupts and some will also be initiators.

We do not use bi-directional (tri-state) busses within our SoC: instead we use dedicated busses and multiplexor trees.

In this section we use the following RTL net names:

• addr[31:0]: Input. Selection of internal address - not all 32 bits will be used,
• hwen: Input. Asserted during a write from host to target,
• hren: Input. Asserted during a read from target to host,
• wdata[31:0]: Input. Data to a target when writing/storing,
• rdata[31:0]: Output. Data read from target is reading/loading,
• interrupt: Output. Asserted by target when wanting attention.

On an initiator the net directions will be reversed.

For simplicity, in this section, we assume a synchronous bus with no acknowledgement signal, meaning that every addressed target must respond in one clock cycle with no exceptions. Hence a cycle acknowledge handshake signal is not needed.

Also we assume only complete words are ever stored, so no byte lane qualifiers for bytes and halfwords are shown.