The figure
shows a 32-bit DRAM subsystem. Four CAS wires are used so that writes to individual byte lanes are possible.
For large DRAM arrays, need also to use multiple RAS lines to save power by not sending RAS
to un-needed destinations. [Detailed wiring details non-examinable]
61: (C) 2008-15, DJ Greaves, University of Cambridge, Computer Laboratory.