Semi-Custom Design Approach

The figure shows a cell from the data book for a standard cell library. This device has twice the `normal' drive power, which indicates one of the compromises implicit in standard cell over full-custom, which is that the size (driving power) of transistors used in a cell is not tuned on a per-instance basis. Mask-programmed gate array has been mostly replaced with the field-programmed FPGA except for analog/mixed-signal niches »TRIAD

Standard cell layout for a Kogge-Stone adder. Taken from a student project (PDF on course web site).

In standard cell designs, cells from the library can freely be placed anywhere on the silicon and the number of IO pads and the size of the die can be freely chosen. Clearly this requires that all of the masks used for a chip are unique to that design and cannot be used again. Mask making is one of the largest costs in chip design.