HOME       UP       PREV       NEXT (Practical Bus Protocols on IP Blocks)  

Classes of On-Chip Protocol

  1. Reciprocally-degrading: such as handshake protocols studied earlier: throughput is inversely proprotional to target latency in terms of clock cycles,
  2. Delay-tolerant: such as AMBA-3 (ARM's AXI) and OCP's BVCI (below): new commands may be issued while awaiting responses from earlier,
  3. Reorder-tolerant: responses can be returned in a different order from command issue: helpful for DRAM access and needed for advanced NoC architectures.
  4. Virtual-circuit flow controlled: (beyond scope of this course): each source has a credit counter controlling how many packets it can send and priority mechanisms ensure responses are returned without deadlock.

Lables or tags need to be added to each transaction to match up commands with responses.

The EACD+ARCH part Ib classes use the 'Avalon' bus on the Altera devices: »Avalon Interface Specifications

For those interested in more detail: »Comparing AMBA AHB to AXI Bus using System Modelling

54: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.