I/O Blocks, Common Interface Nets.

We will consider a number of IP (interlectual property) blocks. All will be targets, most will also generate interrupts and some will also be initiators.

We use no bi-directional (tri-state) busses within our SoC: instead we use dedicated busses and multiplexor trees.

In this section we use the following RTL net names:

• addr[31:0]: Internal address selection within a target,
• hwen: Asserted during a write from host to target,
• hren: Asserted during a read from target to host,
• wdata[31:0]: Input data to a target when written,
• rdata[31:0]: Output data when target is read,
• interrupt: Asserted by target when wanting attention.

On an initiator the net directions will be reversed.

For simplicity, in this section, we assume a synchronous bus with no acknowledgement signal, meaning that every addressed target must respond in one clock cycle with no exceptions.