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Clock Domain Crossing Bridge

A clock-domain-crossing bridge is needed between clock domains.

The basic techniques are the same whether implemented as part of an asynchronous FIFO, a SoC bus bridge or inside an IP block (e.g. network receive front end to network core logic).

The same techniques apply when receiving asynchronous signals into a clock domain.

The following figure illustrates the key design aspects for crossing in one direction, but generally these details will be wrapped up into something like the domain-crossing FIFO shown earlier.

Design principle:
  • Have a one-bit signal that is a guard or qualifier signal for all the others going in that direction.
  • Make sure all the other signals are settled in advance of guard.
  • Pass the guard signal through two registers before using it (metastability avoidance).
  • Use a wide bus (crossing operations less frequent).

Receiver side RTL:

   input clk;  // receiving domain clock
   input [31..0] data; 
   input req;
   output reg ack;

reg [31:0] captured_data; reg r1, r2; always @(posedge clk) begin r1 <= req; r2 <= r1; ack <= r2; if (r2 && !ack) captured_data <= data;

41: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.