Abstract syntax for a synthesisable RTL (Verilog/VHDL) without provision for delays:
datatype ex_t = // Expressions: Num of int // integer constants | Net of string // net names | Not of ex_t // !x - logical not | Neg of ex_t // ~x - one's complement | Query of ex_t * ex_t * ex_t // g?t:f - conditional expression | Diadic of diop_t * ex_t * ex_t // a+b - diadic operators + - * / << >> | Subscript of ex_t * ex_t // a[b] - array subscription, bit selection.Imperative commands (might also include a `case' statement) but no loops.
datatype cmd_t = // Commands: Assign of ex_t * ex_t // a = e; a[x]=e; - assignments | If1 of ex_t * cmd_t // if (e) c; - one-handed IF | If2 of ex_t * cmd_t * cmd_t // if (e) c; else c - two-handed IF | Block of cmd_t list // begin c; c; .. end - blockOur top level will be an unordered list of the following sentences:
datatype s_t = // Top-level forms: Sequential of edge_t * ex_t * cmd_t // always @(posedge e) c; | Combinational of ex_t * ex_t // assign e1 = e2;
|17: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.||Flash Player Upgrade Needed READY|