The following offer guidance relating to common issues. If you don't find your problem listed here, you
should check the lab issues wiki.
You may also want to investigate some common mistakes in C.
- Extra time
If you miss lab sessions (e.g. due to illness) or you really 'just don't get it', we can usually help arrange
extra supervisions in conjunction with your DoS.
- Running the tools on your own machine
If you want to work on the exercises away from the practical
sessions, you can install the Web Edition of the Quartus
tools which needs no license setup beyond registration and works
outside the Cam domain. Take care when mixing the Web edition with the
Subscription edition as the .sof output files (that you program
onto the FPGA) have different names (see 'OpenCore Plus Status' below).
Make sure you aren't programming an old version of your design.
If you need to use the full Subscription version of the tools, access
to the license server for the Subscription version is available from the
cam.ac.uk domain - email theo.markettos at
cl.cam.ac.uk for details.
- Programmer failure - cannot talk to tPad using usb-to-jtag programmer
- Check that you plugged your tPad into the right computer!
The computer that you are using is most likely to be the one
to the right of the monitor. We've been caught out by this
before, particularly late on a Friday afternoon!
- Try unplugging the tPad from the computer and plugging
it in again. You can check to see if it connected
using jtagconfig which will report if a device is
- Check the board is connected and
that SW19 is set
- If you have a problem when using the NIOS II IDE, stop
any NIOS II consoles, such as the one opened by Eclipse: click
the NIOS II Console tab and then the red
stop button to terminate and remove the launch.
- Check that there is a udev rule installed for the USB
device. Often on Ubuntu this is in /etc/udev/rules.d/ but
on the MCS machines it should be in:
If this rule does not exist then it may be installed
during a reboot which, on the MCS machines, also updates
- ...OpenCore Plus Status...Click cancel to stop using OpenCore
Plus IP.... occurs after programming
The most likely cause if that you've brought your project in
from home where you were using the web edition of the tools.
Make sure that you delete the *_time_limited.sof file
otherwise it will be incorrectly picked up by the programmer.
In the programmer window you can click Change File...
to specify which .sof file to use. Failure to use the
correct .sof file will result in the wrong version of the design
being which maked debugging "ineffective"!
- ...instantiates undefined entity...
A reference to a module cannot be resolved. Check the spelling of the module indicated by the message. If the
message concerns a module generated by Qsys, you need to ensure the .qip file has been imported
into your Quartus project. Otherwise, check that you have imported the (System)Verilog files containing the module
definition. You can add files to a Quartus project by going Project | Add/Remove Files in Project.
- Board LEDs display arbitrary pattern
Check you have imported the pin assignments for the board. If not, you will afterwards need to re-compile your
Quartus project and re-program the board. Note that, in case of doubt, re-importing the assignments is fine.
- Quartus fails to start
If the error concerns licence servers, call a demonstrator (during the labs) or email Simon Moore (simon dot moore
at cl dot cam dot ac dot uk). The issue may also be machine specific - try another machine.
- FPGA activity corresponds to a previous design
A new .sof file has been produced, whilst the programmer is still using the old version. Double-click
on the filename in the programming window to modify the path.
- Quartus fitting failed
Check the compilation warnings for implicit nets or dangling wires; the connections
in your design may be incomplete or incorrect.
- Qsys component library empty
Eclipse (NIOS II)
- Fails to create a new project and BSP
When creating a new project and BSP you will see linker errors
if the sdram is not connected to the NIOS processor in Qsys
since the generator script has no place to put your code.
Check your Qsys project that both the data master and the
instruction master bus interfaces on your NIOS are connected
to the SDRAM.
- ...failed elf download...
In your Quartus root module, check the reset input to the instance of your
Qsys component. Since the button signals are active low, it may be your system
is continually being reset.
Also check that the PLL is configured correctly with an input
clock of 50MHz, the main system clock at 100MHz with no phase
shift and the SDRAM clock at 100Mhz with a -3ns (not -3deg or
-3ps) phase shift.
- No output on NIOS JTAG console (i.e. nothing from printf)
First check that you did include a JTAG UART in your Qsys
design, that it is connected up and that the base address
as seen in Qsys matches the base address in system.h
We have found that if your main system PLL has been configured
for a 100MHz input clock (rather than 50MHz as it should be) and
the output clocks are also at 100MHz (i.e. multiply by 1 and
divide by 1) then the resulting clock will actually be 50MHz.
This appears to allow code (your elf file) to download correctly
but no output will be produced.
Another possible cause (which is rarer) is that the board
support package (BSP) has had its default outputs for stdout,
stdin and stderr changed so that they no longer direct input and
output to the NIOS JTAG console. The BSP will need to be edited
to fix this. You may need to ask for help to do this.
- Eclipse crashes on run
You can help to prevent this by stopping any previous NIOS II console before re-launching. This
can be done by clicking the NIOS II Console tab and then the red stop
button to terminate and remove the launch.
- Eclipse project creation failure
Irrespective of failure, Eclipse will probably generate the project folders, preventing you from recreating the
project under the same name. Delete them. In Qsys, check the Avalon Memory Mapped Master, nios2_qsys_0.instruction_master
is connected to the Avalon Memory Mapped Slave, sdram_0.s1. Also check the
base address of sdram_0.s1 is zero. Finally, try recreating the project.
- ...console model invalid...
Your BSP Project is (probably) out-of-sync with respect to the Qsys system. Right click on the BSP project and go NIOS II |
Generate BSP. Then go Project | Clean... and click OK. Now try relaunching. Also try restarting
- ...make Error 1
Check for additional errors and advice. If no further information is given, it is possible the project files
are corrupted; the project (and BSP) will need to be recreated; either use a different name or delete the
project folders from the file system after moving any custom code to a safe location.
- ...error while discovering JTAG connections...
Restart Eclipse. Also see the notes on Programmer Failure in
the Quartus section.