Non-synth continued.

Testbenches commonly uses delays:

  // Typical RTL testbench contents:
  reg clk, reset;
  initial begin clk=0; forever #5 clk = !clk; end   // Clock source 100 MHz
  initial begin reset = 1; # 125 reset = 0; end     // Power-on reset generator

23: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.

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