A megafunction is a pre-built module that performs a commonly required function. This prevents the developer having to write these modules themselves, hence saving a lot of development time. Altera ship several megafunctions with Quartus covering a range of tasks such as a FIFO buffer, arithmetic units - add, multiply, divide etc., several DSP modules, and a lot more besides.

Adding a PLL Megafunction

The tPad provides 2 clock oscillators, one at 50MHz and the other at 27MHz. However, in your designs you may find you need to produce a modified clock signal e.g. with a different frequency or phase. This can be done using a PLL (Phase-Locked-Loop) megafunction.

Begin in Quartus by going Tools | MegaWizard Plug-In Manager from the menu, and when prompted, select Create a new custom megafunction variation. Click Next.

Ensure Cyclone IV E is the device family selected, and Verilog HDL is the output language. The tree view on the left-hand side shows the various megafunctions available. Open up the node marked I/O and select ALTPLL. Finally, give the file to be created a name e.g. pll.v, ensuring it is saved in the working directory for your project. Click Next.

You should now be on page 3 of 10 of the wizard. On this page, set the Device speed grade to 7 and set the frequency of the inclock0 input to 50 MHz. Leave the other settings as default, and click Next.

Un-tick all the boxes on page 4 of the wizard. These features are not required. Click Next until you reach page 8.

You should now be on the page titled c0 - Core/External Output Clock. This page allows you to specify parameters for the first output clock of the component. To change the frequency, you can either select Enter output clock parameters and enter a pair of integers into Multiplication factor and Division factor or select Enter output clock frequency and enter the desired clock rate.

Click Next to specify additional output clocks as required. Otherwise, click Finish to move to page 14 of the wizard, which displays a list of the files that will be created. Click Finish again to create the megafunction. This adds the megafunction to your project. If asked to add Quartus IP files to the project, tick the box and answer yes.

The module definition can be found in the file you specified. An example instantiation of the created component is:

pll altpll(.inclk0(CLOCK_50), .c0(clk));