DRAM controller is typically coupled with a cache or at least a write buffer.
DRAM: high latency and write-back overhead dictate preference for large burst operations.
It is best if clients make available several operations for processing at once: up to number of banks.
It is best if clients can tolerate responses out of order (hence use bus/NoC structure that supports this).
Controller typically contains a tiny CPU to interrogate serial device data.
DRAM refresh overhead has minimal impact on bus throughput.
In the memories folder there is a simple DRAM+Controller TLM model. In the dramsim2 folder there is a TLM wrapper around the Univ-Maryland DRAM simulator. (Not examinable for CST).