NEXT (SoC Example: Helium 210)
Clock Domain Crossing Bridge
A clock-domain-crossing bridge is needed between clock domains.
The basic techniques are the same whether implemented as part of a SoC bus bridge
or inside an IP block (e.g. network receive front end to network core logic).
The same techniques apply when receiving asynchronous signals into a clock domain.
- Have a one-bit signal that is a guard or qualifier signal for all the others going in that direction.
- Make sure all the other signals are settled in advance of guard.
- Pass the guard signal through two registers before using it (metastability avoidance).
- Use a wide bus (crossing operations less frequent).
Receiver side RTL:
input clk; // receiving domain clock
input [31..0] data;
output reg ack;
reg [31:0] captured_data;
reg r1, r2;
always @(posedge clk) begin
r1 <= req;
r2 <= r1;
ack <= r2;
if (r2 && !ack) captured_data <= data;