Some state registers inside an I/O block are part of the programmer's model in that they can be directly addressed with software (read and/or written), whereas other bits of state are for internal implementation purposes.
The general structure of GPIO pins has not changed since the early days of the 6821 I/O controller. A number of pins are provided that can either be input or output. A data direction register sets the direction on a per-pin basis. If an output, data comes from a data register. Interrupt polarity and masks are available on a per-pin basis for received events. A master interrupt enable mask is also provided.
The slide illustrates the schematic and the Verilog RTL for such a device. All of the registers are accessed by the host using programmed I/O.