// // SoC P35 Exercise 4 2011/12 // Exercise 4: Investigation of performance, power, area trade offs. // Please do the following 1. Investigate the timing and power performance figures for your three implementations (2, 3 and 4) of exercise 3 and check their scaling with different sizes of input data. Include figures for total execution time, cache hit ratios, chip area, number of DRAM columns addressed and power consumption. 2. Compare your results to an analytical model of your own creation or results in a published article. This should be one or more simple formula(e) that roughly fit the data you have measured. 3. Optional: for further understanding, make variations to the model, such as: enable and disable the cache(s) or vary their size, policy or clock frequency, add a separate I cache or change the main memory from DRAM to SRAM. Your experiments should help confirm your analytical model and enable you to conclude whether your selected partition was a sensible approach. Perhaps compare with another partition. Note you cannot easily determine power when running directly on the workstation (approach 3 of Exercise 3) so skip that. Full marks will be awarded for a short report (4 pages or so) that includes graphs of power consumption and execution speed and an analytical model that roughly fits. Please give in at least a preliminary report by the published deadline to get feedback. Re-submission to get a higher mark is allowed at any point up to the final deadline at the start of the Easter Term.