//
// SoC P35 Exercise 2 2011/12 
// 




// Please do the following 
  
     1. Create another version of PERIPHERAL_DEVICE which is a coded as a transactional modelling  `target'.
        You may use the TLM-1 style coding and generic payload from the TOY-ESL classes or you may use the
        TLM 2.0 library, as used in the OpenRISC btlm reference design.

        Note: you do not need to include any timing or power annotations.


     2. Write short notes about how processor cores on a single piece of silicon might exchange data
        using message-passing channels rather than using a cache-consistent shared memory. Concentrate
        on how the software interfaces to the hardware, rather than on the details of any on-chip-network.
        Please include at least one of the following: a programmers model specification, some example assembly
        language code that sends and receives a message, a basic RTL implementation, a basic TLM-style implementation.

        Note: You may wish to use real examples (such as TILE64, XMOS or elsewhere) or just make up a basic
        design of your own.  Data messages might typically contain 16 bytes.


     3. Optionally, create a Transactor that, when combined with your answer from Exercise 1 gives something
        that offers the same TLM interface as your answer to part 1 of Exercise 2. In fact, you might wish to do
        this step first.  The Transactor should be a SystemC module.
        


Note: the listed deadline for this exercise was originally Weds 8th but please give in any time before 10:00 am on Friday 12th.


1. http://en.wikipedia.org/wiki/TILE64
2. http://en.wikipedia.org/wiki/XMOS