#include <avr/io.h>
#include <config.h>
#include <serial_ram.h>
#include <spi.h>
#include <util/delay_basic.h>
#include <util/delay.h>

/*

Support for M25P16 2Mbyte flash RAM 


requires definitions of ATMEL ports:

	SPI_PORT		Port for the SPI signals eg PORTB
	SPI_DDR 		DDR for the SPI signals eg DDRB
	SPI_PIN 		Input Port for the SPI signals eg PINB

	SPI_SCK 		Clock from master to slave
	SPI_MOSI   		Data from Master to slave
	SPI_MISO   		Data from slave to master

	RAM_PORT		PORT for the RAM CS signal
	RAM_CS


and RAM registers

	RAM_RDID
	RAM_WREN
	RAM_BE
	RAM_PP
	RAM_RDSR
	
and of functions:

	write_spi_byte
	read_spi_byte

Additionally, RAM_CS must be defined as an output on the appropriate DDR

*/


void read_ram_id(uint8_t* mem_ptr) {

	SPI_PORT &= ~(1<<SPI_SCK);			// make sure start with SCK low 
	SPI_PORT &= ~(1<<SPI_MOSI);
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_RDID);
	mem_ptr[0] = read_spi_byte();
	mem_ptr[1] = read_spi_byte();
	mem_ptr[2] = read_spi_byte();
	RAM_PORT |= 1<<RAM_CS;				// deassert cs 
}



uint8_t read_ram_status() {

	uint8_t status;

	SPI_PORT &= ~(1<<SPI_SCK);			// make sure start with SCK low 
	SPI_PORT &= ~(1<<SPI_MOSI);
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_RDSR);
	status = read_spi_byte();
	RAM_PORT |= 1<<RAM_CS;				// deassert cs 
	return status;
}


void ram_bulk_erase() {
		

	SPI_PORT &= ~(1<<SPI_SCK);			// make sure start with SCK low 
	SPI_PORT &= ~(1<<SPI_MOSI);
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
// enable write 
	write_spi_byte(RAM_WREN);			// write enable instruction 	
	RAM_PORT |= (1<<RAM_CS);			// deassert cs 
	_delay_us(1); 
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_BE);				// bulk erase instruction 
	RAM_PORT |= (1<<RAM_CS);			// deassert cs 
	while (read_ram_status() & 0x01) 
		;	
}


void ram_sector_erase(uint8_t sector) {
		

	SPI_PORT &= ~(1<<SPI_SCK);			// make sure start with SCK low 
	SPI_PORT &= ~(1<<SPI_MOSI);
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
// enable write 
	write_spi_byte(RAM_WREN);			// write enable instruction 	
	RAM_PORT |= (1<<RAM_CS);			// deassert cs 
	_delay_us(1); 
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_SE);				// sector erase instruction 
	write_spi_byte(sector);				// sector erase instruction 
	write_spi_byte(0x00);				// sector erase instruction 
	write_spi_byte(0x00);				// sector erase instruction 
	RAM_PORT |= (1<<RAM_CS);			// deassert cs 
	while (read_ram_status() & 0x01) 
		;	
}


void write_flash_page(uint8_t flash_sector,uint8_t flash_page,uint8_t* mem_ptr) {
	read_write_flash_ram(0,256,flash_sector,flash_page,0,mem_ptr);
}
void read_flash_page(uint8_t flash_sector,uint8_t flash_page,uint8_t* mem_ptr) {
	read_write_flash_ram(1,256,flash_sector,flash_page,0,mem_ptr);
}


void read_write_flash_ram(uint8_t one_read_zero_write,uint16_t bytes_to_readwrite,uint8_t flash_sector,uint8_t flash_page,uint8_t offset,uint8_t* mem_ptr) {

	uint16_t i;

// for ram device, enter and leave with SCK low

	SPI_PORT &= ~(1<<SPI_SCK);
	SPI_PORT &= ~(1<<SPI_MOSI);

	RAM_PORT &= ~(1<<RAM_CS);				// assert cs
	if (one_read_zero_write) {
		write_spi_byte(RAM_READ);
	} else {
// enable write
// write enable instruction	
		write_spi_byte(RAM_WREN);
		RAM_PORT |= (1<<RAM_CS);
		_delay_us(1);
		RAM_PORT &= ~(1<<RAM_CS);
		write_spi_byte(RAM_PP);
	}
	write_spi_byte(flash_sector);
	write_spi_byte(flash_page);
	write_spi_byte(offset);
	for (i=0;i<bytes_to_readwrite;i++) {
		if (one_read_zero_write) {
			mem_ptr[i] = read_spi_byte();
		} else {
			write_spi_byte(mem_ptr[i]);
		}
	}	
	RAM_PORT |= (1<<RAM_CS);
	_delay_ms(40);
	while (read_ram_status() & 0x01) 
		;	
}

// write to the RAM status byte. 0 in bottom bit position = ready 
void write_ram_status(uint8_t status) {

	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_WREN);					// write enable instruction 	
	RAM_PORT |= (1<<RAM_CS);			// deassert cs 
	_delay_us(2); 
	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_WRSR);
	write_spi_byte(status);
	RAM_PORT |= 1<<RAM_CS;				// deassert cs 
	_delay_us(2);
	while (read_ram_status() & 0x01) 
		;	
}


void power_up_flash_ram(void) {

	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_RES);
	RAM_PORT |= 1<<RAM_CS;				// deassert cs 
	_delay_us(30);
}


void power_down_flash_ram(void) {

	RAM_PORT &= ~(1<<RAM_CS);			// assert cs 
	write_spi_byte(RAM_DP);
	RAM_PORT |= 1<<RAM_CS;				// deassert cs 
}