High-Level Synthesis

Manual RTL design expression needs

• Human comprehension of the state encoding,
• Human comprehension of the cycle-by-cycle concurrency, and
• Human accuracy to every low-level detail.

Performing a Time for Space re-folding (i.e. doing the same job with more/less silicon over less/more time) requires a complete redesign at this level!

Optimising schedules in terms of memory port and ALU uses ? Pen and paper?

Can we do better ? Want to use High-Level Synthesis.