NEXT (Partitioning example: An external RS-232/POTS Modem.)
An old example example: The Cambridge Fast Ring two chip set.
Two devices were developed for the CFR local-area network (1983),
illustrating the almost classical design partition required in
high-speed networking. They were never given grander names than the
ECL chip and the CMOS chip. The block diagram for an
adaptor card is shown in the
The ECL chip clocked at 100 MHz and contained the minimal
amount of logic that needed to clock at the full network
clock rate. Its functions were:
- implement serial transmission modulator and demodulator,
- convert from 1 bit wide to 8 bits wide and the other way around,
- perform reception byte alignment (when instructed by logic in the CMOS chip).
The CMOS chip clocks at one eighth the rate and handles the complex
- ECL logic can support analogue line receivers at low additional cost
so can receive the incoming signal directly on to the chip.
- ECL logic has high output power if required (1 volt into 25 ohms) and
so can drive outgoing twisted pair lines directly.
The ECL chip had at least 50 times the power consumption of the CMOS chip.
The CMOS chip had more than 50 times the gates of the ECL chip.
%% these ratios might be closer to 500 to 1.
Rolling forward to 2010, we might make a similar design partition
with a high-performance bipolar subsystem clocking at 4 GHz connected
to a CMOS 'baseband' component running where some small parts operating at 500 MHz and the
remainder at 250 MHz.
- CRC generation
- full/empty bit protocol
- minipacket storage in on-chip RAM
- host processor interface
- ring monitoring and maintenance functions.
Standard parts were used to augment the CFR set: the DRAM
chip incorporates a dense memory array which could not have been
achieved for anywhere near the same cost onboard the CMOS chip and
the VCO (Voltage Controlled Oscillator) device used for
clock recovery was left off the ECL chip since it was
a difficult-to-design analogue component where the risk
of having it on the chip was not desired.
PALs are used to `glue' the network interface itself to a particular
host system bus. Only the glue logic needs to be redesigned when a
new machine is to be fitted with the chipset. PALs have a short
design turn-around time since they are field-programmable.
For a larger production run, the PALs would be integrated onto a
custom variant of the CMOS chip.