A PAL is programmable array logic device. The figure shows a typical device. Such devices have been popular since about 1985. They are really just highly structured gate arrays. Every logic function must be multiplied out into sum-of-products form and hence is achieved in just two gate delays.
The illustrated device has 8 product terms per logic function, and so can support functions of medium complexity. Such devices were very widely used in the 1980' because they could support clock rates of above 100 MHz. Today, FPGA speeds of 200 MHz are common and they also provide special function blocks, such as PCI-e interfaces, so the need for PALs has diminished.
Programmable macrocells enable the output functions to be either registered or combinatorial. Small devices (e.g. with up to 10 macrocells) offer one clock input; larger devices with up to about 100 macrocells are also available, and generally offer several clock options. Often some macrocells are not actually associated with a pin, providing a so called buried state flip-flop. Mini design example: As entered by a designer in a typical PAL language, and part of the fuse map that would be generated by the PAL compiler. Each product line has seven groups of four fuses and produces the logical AND of all of the signals with intact fuses. An `x' denotes an intact fuse and all of the fuses are left intact on an unused product lines in order to prevent the line ever generating a logical one (a gets ANDed with abar etc.). The fuse map is loaded into a programming machine (in a file format known as JEDEC), an unused PAL is placed in the machine's socket and the machine programs the fuses in the PAL accordingly.
PALs achieve their speed by being highly structured. Their applicability is restricted to small finite state machines and other glue logic applications.