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An FPGA (field-programmable gate array) consists of an array of configurable logic blocks (CLBs), as shown in Figure~\ref{fig:fpgaplan}. Not shown is that the device also contains a good deal of hidden logic used just for programming it. Some pins are also dedicated to programming. Such FPGA devices have been popular since about 1990.

Each CLB (configurable logic block) or slice typically contains two or four flip-flops, and has a few (five shown) general purpose inputs, some special purpose inputs (only a clock is shown) and two outputs. The illustrated CLB is of the look-up table type, where the logic inputs index a small section of pre-configured RAM memory that implements the desired logic function. For five inputs and one output, a 32 by 1 SRAM is needed. Some FPGA families now give the designer write access to this SRAM, thereby greatly increasing the amount of storage available to the designer. However, it is still an expensive way to buy memory.

All CLBs within a FPGA generally have the same structure, but FPGAs are available with lower and higher functionality CLBs. The best size of CLB is not yet clear. Some designs of FPGA have a hierarchy of CLB interconnection patterns, giving CLB clusters within clusters. Most designs support special paths for fast carry adders and multiplier structures.

An FPGA is very like a mask-programmed gate array to use. The design flow and CAD tools are virtually identical. However, the expenditure before the designer has the first device in her hands might be 10,000 times lower. The cost of further devices used to be at least 10 times higher than mask-programmed devices, owing to the programming cost and wasted die area devoted to the programming activities. However, modern mask costs make the ASIC and mask-programmed gate array unattractive.

FPGAs tend to be relatively slow, owing to larger die areas than an ASIC equivalent and because the signals pass through hidden logic used only for configuration.

Generally a company will build prototypes and some early production units using FPGAs and then use a drop-in mask-programmed equivalent once the design is mature and sales volumes are very large.

20: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.