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On-chip Busses Summary.

Multiplexing using tri-states is common at the PCB level but active multiplexors result in less energy use for on-chip use.

It is handy if all of the IP blocks to be integrated conform to a common bus bus port standard.

Automatic synthesis of glue logic and memory maps is possible (see elsewhere in these notes).

Formal specifications of bus ports are widely used, assisting in tool automation and ABD.

The AMBA AHB bus from ARM Cambridge was widely used: but is quite complex and had no temporal decoupling.

The OCP BVCI supports temporal decoupling, but requests and responses must not overtake: hence it can cross clock domains and tolerate pipeline stages.

The ARM AXI bus includes tags on each operation for request/response association: hence it is suitable for pipelined, on-chip networks where packet sequencing may vary.

Other busses: The Wishbone bus and IBM CoreConnect bus: used by various public domain IP bocks and various designs (e.g. RTL OR1K). »Wikipedia Wishbone »Core Connect

»GreenSocs Bus `The GreenSocs mission is to enable the ESL community to quickly develop models and tools that can be used together with independence of vendor (whether the vendor is of models or tools). Our scope includes everything from package management for ESL, simple IP blocks, integrations with scripting tools and of course interfaces.'

16: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.