DRAM controller is typically coupled with a cache or at least a write buffer.
DRAM: high latency and write back overhead dictate preference for large burst operations.
It is best if clients make available several operations for processing at once: up to number of banks.
It is best if clients can tolerate responses out of order (hence use bus/NoC structure that supports this).
Controller might contain a tiny CPU to interrogate serial device data.
DRAM refresh overhead has minimal impact on bus throughput.