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Cache Modelling

Depending on our needs, we may want to measure the hit ratio in the I or D caches, or the effect on performance from the misses, or neither, or all such metrics. »[Virtutec Simics.]

So a cache can be modelled at various levels of abstraction:

An instruction cache (I-cache), when modelled, may or may not be accessed by an emulator or instruction set simulator (ISS). For instance, the ISS may use backdoor access to the program in main memory, or it might use JIT (just-in-time) techniques where commonly executed inner loops of emulated code are converted to native machine code for the modelling workstation.

A SystemC cache model will be illustrated in lectures and on course web site or PWF.

23: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.