Often we have two implementations of a combinational circuit to check for equivalence. .latex For example, they might be:
Error sources: manual implementation of one of them, manual edits to synthesiser outputs and EDA tool faults.
Boolean equivalence: do the two functions produce the same output?
Method: Create a MITRE of the two designs using a disjunction of XOR gate outputs.
Then: feed negation of mitre to a SAT solver.
Result: if there are no solutions, designs are equivalent.