However, referring back to the DMA unit behavioural model, we can see that that memory operations are likely to get well out of synchronisation with the real system since this copying loop just goes as fast as it can without worrying about the speed of the real hardware. It is just governed by the number of cycles the read and write calls block for, which could be none. The whole block copy might occur in zero simulation time!
This sort of modelling is useful for exposing certain types of bugs in a design, but it does not give useful performance results.
We shall shortly see how to limit the sequential inconsistencies using a quantum keeper.