We will consider a number of IP (interlectual property) blocks. All will be targets, most will also generate interrupts and some will also be initiators.
We use no bi-directional (tri-state) busses within our SoC: instead we use dedicated busses and multiplexor trees.
We use the following RTL net names:
On an initiator the net directions will be reversed.
For simplicity, in this section, we assume a synchronous bus with no acknowledgement signal, meaning that every addressed target must respond in one clock cycle with no exceptions.