Not all RTL is officially synthesisable, as defined by language standards.
RTL with event control in the body of a thread defines a state machine.
This state machine requires a program counter (PC) register at runtime (implied):
input clk, din; output req [3:0] q; always begin q <= 1; @(posedge clk) q <= 2; if (din) @(posedge clk) q <= 3; q <= 4; end
How many bits of PC are needed ? Is conditional event control synthesisable ? Does the output `q' ever take on the value 4 ?