to insert arbitrary delay figures in our source code, yet some sort of delay is needed to make synchronous hardware
work correctly. The solution is the **delta cycles**.

For correct behaviour of synchronous edge-triggered hardware, the progagation delay of D-types must be greater than their hold time.

Question : How can we ensuse this in a technology-neutral model that does not have any specific numerical delays ?

// Example: swap data between a pair of registers reg [7:0] X, Y; always @(posedge clock) begin X <= Y; Y <= X; end // E.g. if X=3 and Y=42 then Y becomes 3 and X becomes 42. |

Answer: Hardware simulators commonly support the compute/commit or `signal' paradigm for non-blocking updates.

26: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.