One implementation is to have an auxiliary list containing nets, called the pending queue. The net.write(value, when) method checks whether the new time is the same as the current time and if so, instead of inserting an event for the net in the event list, the net is placed on the pending queue and the new value stored in a `next value' field in the net. The kernel is then modified as shown above, to empty the pending queue when the next event would advance simulation time.
Note that committing a pending queue update can wake up a model sensitive to the updated net and cause further events to be generated. All pending updates must be committed atomically and new zero-delay events are added to a fresh pending queue.
Hence, when zero-delay models are active and the output of one feeds another (e.g. a zero delay gate in the clock path), the value of system time, tnow, may not advance for several consecutive delta cycles. Clock generators or other components for which we can put in delay figures operate normally, causing real advances in simulation time.
A net that is to have its updated deferred in VHDL (and SystemC) is called a signal, whereas immediate updates when variables are written to. In Verilog, all nets can be assigned in either way and instead two different assignment operators are provided (called blocking and non-blocking, denoted = and <= respectively).
(As we shall see, a SystemC `sc_signal' is implemented with a current and a next value and it is necessary to use the ` net.read()' method to read the value of a SystemC signal because C++ does not allow override of the read operator.)