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2b/3: Pure RTL : unordered synchronous register transfers.

Two coding styles (it does not matter whether these transfers are each in their own always statement or share over whole clock domain):
      always @(posedge clk)  a <= b ? c + d;
      always @(posedge clk)  b <= c - d;
      always @(posedge clk)  c <= 22-c;
      always @(posedge clk) begin
        a <= b ? c + d;
        b <= c - d;
        c <= 22-c;

Typical example (illustrating pure RT forms):

    module CTR16(mainclk, din, o);
      input mainclk, din;
      output o;
      reg [3:0] count, oldcount;
      // Add a four bit decimal value of one to count
      always @(posedge mainclk) begin
          count <= count + 1;
          if (din) oldcount <= count; // Is `if' pure ?

     // Note ^ is exclusive-or operator
     assign o = count[3] ^ count[1];


Registers are assigned in clock domains (one shown called `mainclk').

In a strict form of this pure RTL, we should not use `if', so when we want a register to sometime retain its current value we must assign this explicitly, leading to forms like this:

   oldcount <= (din) ? count : oldcount;

8: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.