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Folding, Retiming & Recoding Continued

Flip-flop migration does alter state encoding.

It exchanges delay in one path delay for delay in another.

A sequence of such transformations can lead to a shorter critical path overall. In the following example, the first migration is a local transformation that has no global consequences:

Before:               Migration 1:             Migration 2 (non causal):
  a <= b + c;            b1 <= b; c1 <= c;         q1 <= (dd) ? (b+c): 0;
  q <= (d) ? a:0;        q <= (d) ? b1+c1:0;       q  <= q1;

The second migration, that attempts to perform the multiplexing one cycle earlier will require an earlier version of d, here termed dd that might not be available (e.g. if it were an external input we need knowledge of the future).

An earlier version of a given input can sometimes be obtain by delaying all of the inputs (think of delaying all the inputs to a bookmakers shop), but this cannot be done for certain applications where system response time (in-to-out delay) is critical.

Problems arising:

Circuits containing loops (proper synchronous loops) cannot be pushed with a simple algorithm since the algorithm loops.
External interfaces that do not use transactional handshakes (i.e. those without flow control)(see later) cannot tolerate automatic re-timing since the knowledge about when data is valid is not explicit.
Many structures, including RAMs and ALUs, have a pipeline delay, so the hazard on their input port needs resolving in a different clock cycle from hazards involving their result values.

but retiming can overcome structural hazards (e.g. the `write back' cycle in RISC pipeline).

Other rewrites commonly used: automatically introduce one-hot and gray encoding, or invert for reset as preset.