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DJIP Blocks - Toy IP Blocks.

A high-level model of the nominal processor:

The MPhil course work will use the ORP 1K processor and not this nominal processor.

A library of SystemC IP blocks that can be used by various targets in different classes:

Futher devices were added during lectures : DRAM controller, cache and DRAM.

TLM (transactional-level modelling) versions of example IP blocks:

The above TLM examples use the TLM 1.0 style since this is easier to understand at first glance.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.