NEXT (Basic Bus: One initiator.)
SoC DRAM and Bus/NoC Structures.
The delay and power problem, physical parameters:
Speed of light on silicon and on a PCB is 200 metres per microsecond.
A clock frequency of 2 GHz has a wavelength of 2E8/2E9 = 10 cm.
Synchronous digital clock domain requires connections to be less
than (say) 1/10th of a wavelength.
RC time constants must also be overcome, so need to register a signal
in several D-types if it passes from one corner of an 8mm chip to the other!
Can have several thousand wires per millimetre per layer: fat busses are attractive.
DRAM is several centimeters away from the SoC and has significant internal delay.
Need to use protocols that are tolerant to registers (4P H/S degrades with reciprocal of delay).
But first let's revist the simple hwen/rwen system used in the 'socparts' section.