The AMBA AHB bus from ARM Cambridge was widely used: but is quite complex and has no temporal decoupling.
The BVCI supports temporal decoupling, but requests and responses must not overtake: hence it can cross clock domains and tolerate pipeline stages.
The ARM AXI bus includes tags on each operation for request/response association: hence it is suitable for pipelined, on-chip networks.
The Wishbone bus and IBM CoreConnect bus: used by various public domain IP bocks and various designs (e.g. RTL OR1K). »Wikipedia Wishbone »Core Connect
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