CMOS delay is inversely proportional to supply voltage.
Voltage to a region may be varied dynamically. A higher supply voltage (at fixed f) uses more power (square law) but allows a higher f.
Operating region of the frequency/voltage curve is roughly linear.
But, logic with higher-speed capabilities is smaller which means it consumes greater leakage current which is being wasted while we are halted.
Let's only raise VCC when we ramp up f.
But Zeno applies still: always aim for a close to unity and a low work rate.
Overall: power will then have cubic dependence on f. So we achieve peak performance under heavy loads and avoid cubic overhead when idle.
Combinational logic cannot be clock gated (e.g. PAL and PLA). For large combinational blocks: can dip power supply to reduce static current when block is completely idle (detect with XORs).